Field-Programme Gate Array (FPGA) Design Engineer
Location | Scotland Glasgow Gartcosh - Glasgow |
Company name | Innovate Recruitment Ltd |
Category | Engineering |
Contract | Permanent |
Full/Part time | Full time |
Salary | £ 35000 - £65000/annum |
Field-Programme Gate Array (FPGA) Design Engineer Location: Glasgow Salary: £35,000 to £65,000 (depending on experience) Our client, a world class innovator, plays a vital role in designing, manufacturing, supplying, and providing continuous support throughout the lifespan of nuclear propulsion products and systems. This contribution is crucial for sustaining the Royal Navy’s submarine fleet and overseeing the management throughout their entire lifecycle. In a submarine’s role, you will work on diverse technical challenges throughout the product life cycle. Shape your career as an engineer, specialist, or leader, with full support for your technical development, including mentoring for chartered engineer status. You will become a part of the safety critical firmware development team, contributing across all design phases using agile SCRUM methods and employing state-of-the-art toolsets. Training will be provided as needed, equipping you with the skills necessary to develop requirements, architectures, designs, and HDL code for controls firmware applications crucial for safeguarding and monitoring nuclear propulsion plants. You will also contribute to developing custom software toolsets for equipment firmware, addressing high safety integrity requirements. This presents opportunities within the firmware team for career growth in technical management, team leadership, or specialistion. The team provides a chance to become and expert in using cutting-edge toolsets. Key Responsibilities: You’ll adhere to a firmware development lifecycle based on DevOps principles to fulfil customer requirements by: * Obtaining high-level firmware requirements using DOORS. * Creating architectural designs. * Identifying low level requirements and detailed designs. * Writing VDL and Verilog HDL code using Sigasi Studio. * Simultating HDL designs at unit, integration and system level using Mentor Graphics QuestaSIM. * Conducting synthesis, place and route, and static timing analysi